The present invention relates generally to memory systems and in particular, to flash memory array systems and methods for producing a charge pump circuit, wherein a voltage detection circuit (e.g., analog to digital converter, digital thermometer), may be used to measure the VCC applied to the charge pump circuit, along with variable pumping capacitance network compensation circuitry to conserve power, and to reduce the ripple and noise in the output voltage. The modulated charge pump voltage may be applied to a wordline or bitline, for example, for program or erase mode operations of memory cells.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read or program operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
For a read operation, a certain voltage bias is applied across the drain and source of the cell transistor. The drain of the cell is coupled to the bitline, which may be connected to the drains of other cells in a byte or word group. The voltage at the drain in conventional stacked gate memory cells is typically provided at between about 0.5 and 1.0 volts in a read operation. A voltage is then applied to the gate (e.g., via the respective wordline) of the memory cell transistor in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed cell threshold voltage (VT) and an unprogrammed cell threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
More recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The bitline (drain), and wordline (gate) voltages required for dual bit memory cells is typically higher than that of single bit, stacked gate architecture memory cells, due to the physical construction of the dual bit cell.
In these semiconductor applications, a charge pump sometimes is used to increase a small input, or supply voltage (for example, VCC) to a larger voltage that is passed to the word lines or bit lines of the semiconductor memory devices. For example, some dual bit memory cell architectures require about 9.5 volts to properly bias the word lines, about 6 volts for the bitline or drain of such cells, and between xe2x88x926 to xe2x88x928 volts for negative erase voltages, for the various memory operations discussed. These voltages which are all higher than the applied supply voltage, are all created and fed by charge pumps to increase the supply voltage to the output voltage desired. These voltages affect the reading and writing of data from/to the memory device. The voltage is increased by channeling the relatively small input voltage through a series of stages. The more stages a charge pump has, the greater the resulting output voltage.
Because these charge pump voltages applied to the memory cell are derived from the memory device supply voltage (VCC), the ability to provide the higher voltage required for the newer dual bit memory cells may be impaired when the supply voltage is at or near lower rated levels. In addition, low power applications for memory devices, such as cellular telephones, laptop computers, and the like, may further reduce the supply voltage available.
Currently, conventional charge pumps are constructed using several bootstrap capacitors having the same capacitance C at each respective node of the charge pump. A bootstrap capacitor is defined as the capacitor connected to each respective node of a charge pump. As the required voltages for applications increases, the number of stages necessary to generate the higher output voltages also increases. However, as the number of stages is increased, the efficiency of the charge pump has been found to decrease.
FIG. 1 provides an illustration of a conventional charge pump. As shown, the conventional charge pump 100 has a number of stages (stage 1 thru stage n). The charge pump 100 has at its input, a voltage, VCC which is transmitted through a diode 115 to a first node (node 1) including a first bootstrap capacitor 120 having a capacitance C. A second node (node 2) is connected to the first node (node 1) via a diode 125 and also has a second bootstrap capacitor 130 having a capacitance C. The output of node 2 is then passed through a number of subsequent nodes, identical to previously described nodes 1 and 2, that also include a bootstrap capacitor having a capacitance value C that is substantially identical to the capacitance value C present at nodes 1 and 2. Finally, the conventional charge pump has an output terminal, VOUT, also having a capacitor 160 having a total capacitance CL+P which is defined as being the load capacitance CL of the load connected to the output of the pump and a parasitic capacitance CP inherent in the transmitting means of the conventional pump. As stated above, the bootstrap capacitance of the various nodes of circuit 100 in prior art FIG. 1 all have value C.
In the prior art example of FIG. 2, a conventional two stage charge pump 200 is illustrated with large capacitor values to accommodate the lowest power supply level, and the addition of a shunt regulator 270 attached at the conventional point of the charge pump output 280, to reduce the output when the supply or the output voltage is higher than a target value. As in FIG. 1, the charge pump 200 of FIG. 2 includes an input 210 coupled to an input voltage such as the supply voltage VCC. The input 210 is coupled to a first stage, via a diode 215, which is also coupled to a first stage node (node 1) including a capacitor 220 having a capacitance C1.
The first stage is further connected to a second stage, via a diode element 225, including a second and final stage node (node 2) having a bootstrap capacitor 230 having a capacitance C2. The final stage node (node 2) is coupled through a diode 240 to a load capacitor 260 having a capacitance value CLOAD, and to the shunt regulator 270. The shunt regulator 270 produces a regulated version of the charge pump output VOUT 280.
Also connected to each stage of the charge pumps of FIGS. 1 and 2, are non-overlapping clock phase inputs CLK and CLK NOT, which oscillate from 0 to VCC. The clock phase inputs insure that adjacent charge pump nodes are either being charged by a previous node or is charging a subsequent node.
The shunt regulator 280 regulates the charge pump output by partially shorting to ground that portion of the charge pump output which is greater than a desired voltage level. In this conventional method, large capacitor values may be used to compensate for the lowest power supply voltage. However, when the VCC is not at its lowest level, the use of large capacitor values wastes power supply charge which may be simply shorted to ground through the shunt regulator, resulting in an overall loss of pump efficiency.
The output of the charge pump 280 and the shunt regulator 270 experience a ripple voltage signal from the charge and discharge cycles, with a period which matches the clock cycle period. The ripple voltage level on the output rises during a charge cycle, and drops again as a function of the RC discharge of the load and the load capacitance CLOAD 260. The ripple voltage level rises during the charge cycle, until the shunt regulator determines that an over-voltage condition or target regulation voltage has been reached, wherein the shunt regulator shunting transistors begin to conduct and shunt the over-voltage charge to ground. Because of the internal regulation feedback and response time delays within the shunt regulator, the shunting transistors will not be able to react immediately to the over-voltage level, thereby causing the charge pump voltage to continue to rise beyond the target regulation voltage before the shunting transistors can respond with adequate conduction. Given the typical feedback-response delay of the shunt regulator 270, the conventional charge pump 200 will produce an increased ripple magnitude (e.g., about 400 mV P-P ripple at about 9 volt output) at the output 280 when the input supply voltage 210 is high.
Additionally, noise spikes and valleys are produced on the output 280 as the shunting transistors in the shunt regulator 270 discharge the over-voltage on the charge pump capacitors to ground. Thus, greater supply levels result in higher charge pump output voltage peaks, which result in larger noise spikes and valleys at the regulator output 280, increased power consumption and reduced overall system efficiency.
In a prior art flash memory device, charge pump circuits apply a pumped voltage, for example, to the wordline for program mode operations of memory cells. VCC variations are typically reflected in the output of the charge pump circuit in terms of increased ripple and noise. In addition, at high VCC voltages, the charge pump circuit and shunt regulator circuit together as a system exhibit increased power consumption and reduced system efficiency. Additionally, most device applications seek to consume a minimum of power from the supply, particularly in battery and other portable power device applications this is important. Accordingly, there is a need for a low power, low noise means of compensation for the variations in the VCC supply applied to the charge pump circuit, while maintaining a simple regulator design.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention, Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a novel charge pump circuit where one or more individual stages of the charge pump is characterized by having a variable bootstrap capacitance value which is varied as a function of the input supply voltage.
In the present invention of flash memory array systems and methods for producing a charge pump circuit, the application of a voltage detection circuit (e.g., analog to digital converter, digital thermometer) may be used to measure the value of VCC applied to a charge pump circuit which may be used to generate a charge pump voltage for various operations of memory cells. VCC variations are typically reflected in the output of the charge pump circuit which is supplied to a charge pump regulator which is then supplied to the wordline or bitline of the flash memory array. By compensating for the variations in the VCC supply applied to the charge pump circuit, power consumption is reduced, and the output voltage and peak-to-peak noise variations are limited, thereby enabling a more efficient, low power voltage for the wordlines or bitlines. These features are provided by a charge pump including an input means for providing an input voltage, an output means for delivering an output voltage which is a boosted function of the input voltage, and multiple stage means, connected between the input and output means which generate the modified signal. The multiple stage means also include a plurality of capacitance means, wherein each respective one of the capacitance means has a value which may be varied as a function of the input voltage.
An advantage of the present invention is the ability of the charge pump and shunt regulator system to produce a lower noise output, as compared to conventional charge pump and regulator systems without compensation. In the conventional system, a high input supply level produces a bigger over-voltage on the output of the charge pump. Large noise spikes and valleys are produced at the shunt regulator output at high supply voltage conditions.
A feature of the charge pump of the present invention is that it requires less power than conventional charge pumps, as only the capacitors which are needed to maintain the desired output voltage are charged as a function of the input supply voltage, thereby substantially less power is utilized in the output charge pump regulator.
Another feature of the charge pump of the present invention is that it is more efficient than conventional charge pumps, in that the total power required to produce a desired output voltage is minimized by the ability to vary the capacitance of the bootstrap capacitor values within the stages which are varied as a function of the input supply voltage.
According to one aspect of the present invention, a voltage value associated with the VCC supply voltage is ascertained, for example, using an A/D converter. The determined voltage value is then used to compensate or otherwise adjust a variable bootstrap capacitor network capacitance value associated with one or more stages of a charge pump circuit. For example, a digital word representing the detected VCC voltage value is used to vary effective capacitance values within the capacitor networks of the charge pump circuit. Consequently, the present invention provides a low power, efficient, low noise charge pump output voltage, for example, a charge pumped wordline or bitline voltage, which facilitates an accurate operation of flash memory cells despite fluctuations in the VCC supply voltage.
The aspects of the invention find application in devices which include dual bit memory cells requiring higher bitline and wordline voltages than single bit cells, and in association with memory devices employed in varying supply voltage and low power applications.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.